The underlying mechanism that QEMU uses to connect to external simulation environments is through remote-port (RP). QEMU and the RTL or SystemC Simu lator run on different processe s enabling a less intrusive and much more flexible integration between your exist ing mixed simulation environment and QEMU.
The figure below gives a high level overview of the key components. Your IP must be written in either Verilog or System C. Xilinx exposes a SystemC/TLM interface to conne ct QEMU, which models the hardened Processing System (PS) of any Zynq-based or Versal ACAP product, to a model of your own IP instantiated in the Programmable Logic (PL). This feature enables you to model lar ge and complex systems right fr om the get-go. You can use Xilinx QEMU to connect and drive mixed simulat ion environments using the included remote-port framework.
Qemu fpga simulation license#
(Accellera's SystemC Reference Simulation Env ironment is free and under the Apache v2 License as of 2016). Please see the SystemC page of Accellera’s website for further details and a demo with Accellera 's Open Source SystemC Reference Simulat ion Environment. Feel free to use our libSystemCTLM-SoC to interface your simulation environment to Xilinx' s QEMU. This feature is provided "as-is" and under an open source license model. This feature is predominantly su itable for experienced develope rs in SystemC/TLM and integration with mixed simulatio n environments.
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